|Final Version Due:||2011/01/31|
DPA Contest v2
Dr. Guillaume Duc
Département Communications et Electronique
Telecom ParisTech (ENST), France
The DPA Contest v2 is organized by the VLSI research group from the COMELEC department of the Télécom ParisTech french University. Its is a continuation of the first version whose results were announced during the CHES09 conference.
The goal of this initiative is to make it possible for researchers to compare in an objective manner their different attack algorithms. As this was impossible yesterday, because traces made by different laboratories are too different (acquisition platform sensitivity, cryptographic algorithm implementation, board's noise...), the DPA contest is an initiative towards an international benchmarking reference. Also, we expect significant advances or even breakthroughs to be stimulated by this peer-reviewed contest.
DPA contest V3 and SASEBO-W for DPA Contest V4
Announcement & Presentation
The DPA contest v3 is going to be started, where the target of attack is a real AES circuit on the SASEBO-GII board developed by AIST and Tohoku University. The main purpose of the third contest is to accumulate techniques and know-how for power and EM waveform acquisition, while the previous contests compare the attack algorithms.
The brand-new SASEBO-W board will soon be come up for the fourth contest, which has IC card R/W functionalities. Various hardware and software have also been developed to support side channel attack experiments on the SASEBO boards. We will get a quick overview of the SASEBO project.